1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to suppression of metal hillocks in contact holes for a multi-level interconnection structure.
2. Description of the Background Art
With reference to FIGS. 30 through 36, a brief description will now be given on a method of suppressing an excessive metal deposition (hillock) in a contact hole 4P for a background art multi-level interconnection structure.
FIG. 30 is a schematic cross-sectional view of an excessive metal deposition (hillock) in a contact hole. FIGS. 31 through 36 are cross-sectional views showing fabrication steps wherein such an excessive metal deposition (hillock) is formed.
In FIGS. 30 through 36, the reference character 2P designates lower metal interconnect layers (e.g., AlCu interconnect wires); 2PA designates an upper metal interconnect layer; 3P designates a SOG (spin on glass) layer; 4P designates a contact hole (connect hole) for connecting the upper and lower metal interconnect layers; 5P designates an interlayer dielectric film (e.g., TEOS oxide film); 7P designates an insulation film (specifically a SiO.sub.2 film) serving as a base; 8P designates tungsten; 9P designates barrier metal; and 23 and 24 designate an excessive metal deposition (hillock) in the contact hole and a metal void, respectively, which are the problems of the background art.
The process and reason why the excessive metal deposition (hillock) is created in such a contact hole will be described with reference to the cross-sections of FIGS. 31 through 36 which illustrate the fabrication steps. The process steps prior to the metal interconnection formation, that is, the formation of a transistor, are not illustrated and described in FIG. 31.
First, the Al interconnect wires 2P as an example of the metal interconnect wires are formed on the insulation film 7P serving as the base. The formation of the Al interconnect wires 2P comprises depositing AlCu or AlSiCu over the insulation film 7P by sputtering, performing etching by photolithography using a resist which causes predetermined portions of the AlCu or AlSiCu to be left (FIG. 31), and depositing the interlayer dielectric film 5P (2000 to 5000 angstroms) to entirely cover the Al interconnect wires 2P (FIG. 32). A TEOS oxide film is then used, for example. Next, the SOG (spin on glass) film 3P is applied to the entire top surface to fill a gap in the interlayer dielectric film 5P formed on the Al interconnect wires 2P as illustrated in FIG. 33. Then, the SOG film 3P is sintered by annealing. The SOG film 3P builds up in a corner portion of an open region (a region wherein the metal interconnect wires are widely spaced apart from each other) of the Al interconnect wires 2P to provide a gentle slope of the step.
The interlayer dielectric film 6P (10000 to 25000 angstroms) (a TEOS oxide film in this case) is deposited over the top surface, and is then flattened by the CMP (chemical mechanical polishing) technique to provide a structure shown in FIG. 34. In the CMP technique described herein, the TEOS oxide film is deposited to a thickness several times greater than the height of the step of the metal interconnect wires, and is then polished to a desired thickness.
Referring to FIG. 35, the contact holes 4P are formed in predetermined regions by photolithography and etching. At the time when the contact holes 4P are formed, the excessive metal deposition (hillock) 23 in the contact hole 4P and the metal void 24 as shown in FIG. 36 are not present.
Finally, the contact holes 4P are filled with metal. The tungsten plug technique (filling the contact holes 4P using blanket WCVD) is described herein. For filling the contact holes 4P with the tungsten 8P, an oxide film (not shown) is removed by inert gas (e.g., Ar) or nitrogen gas sputter etching and degassing (lamp heating) is performed for removing gases such as H.sub.2 O and H.sub.2 from the SOG layer 3P in a sputtering system. The metal interconnect wires 2P softened by heat generated during the degassing and stresses f1p and f2p caused by the thickness of the TEOS oxide film 6P create the excessive metal deposition (hillock) 23 and the metal void 24. In general, the commonly used degassing is an RTA (rapid thermal annealing) and the like. After the degassing, the barrier metal 9P (e.g., TiN film or Ti film) having a thickness of 200 to 3000 angstroms is deposited. The tungsten 8P is grown in the contact holes 4P and on the first interlayer dielectric film 6P by the CVD process of the tungsten 8P, and is then etched back so that only the tungsten 8P in the contact holes 4P is left. The upper metal interconnect wire 2PA is deposited for electrical connection. During the above described degassing, the excessive metal depositions (hillocks) 23 in the contact holes 4P and the metal void 24 are formed.
The background art multi-level interconnection structure constructed as above described presents drawbacks to be described below. As described with reference to FIG. 30, the metal interconnect wires 2P softened by the heat generated during the degassing and the stresses f1p and f2p of the interlayer dielectric film 6P having a great thickness formed on upper and side portions of the metal interconnect wires 2P create the excessive metal deposition (hillock) 23 and the metal void 24. Such excessive metal depositions (hillocks) 23 of the metal interconnect wires 2P in the contact holes 4P cause voids in the metal interconnect wires connected to the contact holes 4P, the unevenness of the barrier metal 9P during the formation of the plug of the tungsten 8P, and the abnormal growth and filling failure of the tungsten 8P. These drawbacks also result in the degradation of the electrical characteristics of the tungsten 8P, and the decrease in yield of the device.
For instance, the stresses f1p and f2p of the upper interlayer dielectric film 6P having the great thickness shown in FIG. 30 propagate through the SOG film 3P to the lower interlayer dielectric film 5P, and are consequently applied to the sides of the metal interconnect wires 2P. The application of the stresses f1p and f2p of the thick interlayer dielectric film 6P formed on the upper and side portions of the metal interconnect wires 2P causes the metal hillock 23 and the metal void 24. The result is the unevenness of the barrier metal 9P during the formation of the plug of the tungsten 8P in the contact hole 4P, and the abnormal growth and filling failure of the tungsten 8P.
In this manner, the heat generated during the degassing for fabrication of the multi-level interconnection structure and the stresses caused by the thickness of the interlayer dielectric film create the metal hillock and metal void. These drawbacks result in the unevenness of the barrier metal during the formation of the plug of the tungsten, the abnormal growth and filling failure of the tungsten, the degradation of the electrical characteristics of the tungsten, and the decrease in yield of the device.